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92910 sy/d0909 sy pc 20091028-s00001 no.a1610-1/31 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LV71081E overview the LV71081E is for video/audio signal input/output interface of dvd recorder. functions ? video audio canal sw ? s signal 3 input switch ? 6db amplifier ? 6mhz/12mhz/27mhz-lpf / 6mhz /12mhz/27mhz low pass filter ? 6ch video driver (av1, av2, line output, r?g?b output) ? video signal detection ? composite sync output specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max 6.0 v maximum supply voltage 2 v cc max 13.0 v allowable power dissipation pd max ta 75 c mounted on a specified board * 1200 mw operating temperature topr -20 to +75 c storage temperature tstg -40 to +150 c * mounted on a specified board : 114.3mm 76.1mm 1.6mm, glass epoxy bi-cmos ic video/audio signal io interface of dvd recorder orderin g numbe r : ena1610a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV71081E no.a1610-2/31 recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage 1 v cc 5.0 v recommended supply voltage 2 v cc 12.0 v operating supply voltage range 1 v cc opg 4.5 to 5.3 v operating supply voltage range 2 v cc opg 11.1 to 12.5 v electrical characteristics at ta = 25c, v cc = 2.8v input signal out ratings parameter symbol point signal freq point test condition min typ max unit current dissipation 1 (5v) i cc 1 pin6, 8, 25, 40 flow in current when non-signal 97.7 115.0 132.2 ma current dissipation 2 (all5v) i cc 2 pin42, 84, 94 flow in current when non-signal 20.0 23.0 26.0 ma current dissipation 3 (11.6v) i cc 3 pin46 flow in current when non-signal 18.7 22.0 25.3 ma video canal sw part output voltage 1 vdcc 26 28 av1, av2-out (sync tip) 0.3 0.5 0.7 v voltage gain vgc 100k 26 28 v in = 1vp-p, av1, av2-out 5.5 6.0 6.5 db frequency characteristics vfc 26 28 v in = 1vp-p, f = 10mhz/100khz -1.0 0.0 +1.0 db differential gain dgc 26 28 v in = video : 1vp-p -1 0 +1 % differential phase dpc 26 28 v in = video : 1vp-p -1.5 0 +1.5 c cross-talk ctc 4.43m 26 28 selected input = gnd non-selected input = 1vp-p, f = 4.43mhz -60 -50 db picture s/n vsnc 26 28 v in = video (50%white) -70 -65 db maximum output level v o maxc 26 28 output level ar which the linearity of avi-out (pin 26) and av2-out (pin 28) exceeds 1%. v in = linearity (lamp) signal output level at linearity 1% 2.8 3.0 vp-p video input sw part output voltage 1 vdci1 83 co mposite (sync-tip) 0.8 1.0 1.2 v output voltage 2 vdci2 83 y (sync-tip) 0.8 1.0 1.2 v output voltage 3 vdci3 81 chroma (center) 1.8 2.1 2.4 v voltage gain 1 vgi1 100k 81 83 v in = 1vp-p, load = 10k -0.5 0.0 +0.5 db voltage gain 2 vgi2 100k 85 v in = 1vp-p, load = 10k (slicer output only) 5.5 6.0 6.5 db frequency characteristics vfi 81 83 v in = 1vp-p, f = 10mhz/100khz -1.0 0.0 +1.0 db differential gain dgsw 83 v in = video :1vp-p -1 0 +1 % differential phase dpsw 83 v in = video :1vp-p -1.5 0 +1.5 c cross-talk ctc 4.43m 81 83 selected input = gnd non-selected input = 1vp-p, f = 4.43mhz -60 -50 db picture s/n vsnc 83 v in = video (50%white) -66 -60 db maximum output level v o maxsw 83 output level when the linearity of pin 83 exceeds 1%. v in = linearity (lamp) signal output level at linearity 1% 1.8 2.0 vp-p continued on next page.
LV71081E no.a1610-3/31 continued from preceding page. input signal out ratings parameter symbol point signal freq point test condition min typ max unit video driver part output voltage 1 vdcd1 95 97 99 9 12 17 rgb (pedestal) 0.3 0.5 0.7 v output voltage 2 vdcd2 93 14 23 y (sync tip) 0.5 0.7 0.9 v voltage gain 1 vgd 100k v in = 1vp-p, line output : 2 drives, scart output: dc directly-coupled single drive note 1) 5.5 6.0 6.5 db frequency characteristics 1 vfd1 v in = 1vp-p, f = 6mhz/100khz when 6mhzlpf is selected -1.5 0.0 +1.5 db frequency characteristics 2 vfd2 f = 27mhz/100khz when 6mhzlpf is selected -35 -25 db frequency characteristics 3 vfd3 f = 12mhz/100khz when 12mhzlpf is selected -1.5 0.0 +1.5 db frequency characteristics 4 vfd4 f = 54mhz/100khz when 12mhzlpf is selected -40 -30 db group delay vgdd1 f = 6mhz/100khz when 6mhzlpf is selected 20 35 ns mute attenuation vmud v in = 1vp-p, f=4.43mhz -60 -50 db differential gain dg1 91 93 23 v in = video : 1vp-p -1 0 +1 % differential phase dp1 91 93 23 v in = video : 1vp-p -1.5 0 +1.5 c cross-talk ctd 4.43m v in = 1vp-p, f = 4.43mhz, driver output terminated with 75 -60 -50 db picture s/n vsnd v in = video (50%white) -70 -65 db maximum output level 1 v o maxd1 9 12 17 output level when the linearity of pins 9, 12, and 17 exceeds 1%. v in = linearity (lamp) signal output level at linearity 1% 2.8 3.0 vp-p maximum output level 2 v o maxd2 14 19 23 output level when the linearity of pins 14, 19, and 23 exceeds 1% v in = linearity (lamp) signal output level at linearity 1% 2.6 2.8 vp-p maximum output level 3 v o maxd3 7 11 22 output level at which the linearity of pins 7, 11, and 22 exceeds 1% v in = sin 10khz output level at linearity 1% 2.0 2.5 vp-p sync-sep part c.sync output high voltage vcsh 86 4.3 4.7 5.0 v c.sync output low voltage vcsl 86 0 0.3 0.6 v c.sync output delay time tdcs 86 note 2) 1.0 1.7 2.4 s c.sync output pulse width twcs 86 note 2) 3.2 4.2 5.2 s v.sync output high voltage vvsh 82 4.3 4.7 5.0 v v.sync output low voltage vvsl 82 0 0.3 0.6 v note 1) the line output can drive two systems through capacit ive coupling while the scart output drives only one system through dc direct coupling. note 2) when pin 10 is open continued on next page.
LV71081E no.a1610-4/31 continued from preceding page. input signal out ratings parameter symbol point signal freq point test condition min typ max unit v.sync output delay time tdvs 82 note 2) 7 15 25 s v.sync output pulse width twvs 82 v in = pal video : 1vp-p note 2) 125 155 185 s v.det output high voltage vdeth 90 4.3 4.7 5.0 v v.det output low voltage vdetl 90 0 0.3 0.6 v audio canal switches part maximum output level v o maxc 71 to 74 av1, av2-out (l, r) bw = 400 to 30khz output level at f = 1khz, thd = 1% 2.2 2.5 vrms channel balance cvsw 71 to 74 v in = 2vrms, f = 1khz lch gain-rch gain -1.5 0.0 +1.5 db total harmonic distortion thdac 71 to 74 v in = 2vrms, f = 1khz, bw = 400 to 30khz 0.003 0.01 % output noise voltage vnac 71 to 74 rg = 0 , bw = jis-a -100 -80 dbv mute attenuation vmuac 71 to 74 v in = 2vrms, f = 1khz, bw = jis-a 20log (v out /v in ) -90 -75 db input impedance z in 80 100 120 k cross talk between channel and selctors ctsw 71 to 74 v in = 2vrms, f = 1khz rg = 0 , bw = jis-a -110 -80 db tuner gain g tu 71 to 74 v in = 0.5vrms 10.0 12.0 14.0 db output off set voltage v ofset 71 to 74 off set voltage at the time of changeover sw. -20 0 +20 mv audio adc block voltage gain 1 vga1 78 79 v in = 1vrms, f = 1khz, evr = 0db serial control select 6db. 4.5 6.0 7.5 db voltage gain 2 vga2 78 79 v in = 1vrms, f = 1khz, evr = 0db serial control select 5.5db. 4.0 5.5 7.0 db voltage gain 3 vga3 78 79 v in = 1vrms, f = 1khz, evr = 0db serial control select 5db. 3.5 5.0 6.5 db voltage gain 4 vga4 78 79 v in = 1vrms, f = 1khz, evr = 0db serial control select 0db. -1.5 0.0 +1.5 db channel balance cvvr 78 79 v in = 2vrms, f = 1khz, amp = 5.5db, aevr = -12db lch gain-rch gain -1.5 0.0 1.5 db maximum output level v o maxi 78 79 adc-out (l, r), amp = 0db, evr = 0db bw = 400 to 30khz output level at f = 1khz, thd = 1% 2.2 2.5 vrms total harmonic distortion thdai 78 79 v in = 2vrms, f = 1khz, amp = 5.5db, evr = -12db bw = 400 to 30khz 0.002 0.005 % note 2) when pin 10 is open continued on next page.
LV71081E no.a1610-5/31 continued from preceding page. input signal out ratings parameter symbol point signal freq point test condition min typ max unit output noise voltage vnai 78 79 amp = 5.5db, evr = -12db rg = 0 , bw = jis-a -100 -80 dbv cross talk between channel and selctors ctvr 78 79 v in = 2vrms, f = 1khz, amp = 5.5db, evr = -12db rg = 0 , bw = jis-a -110 -80 db max attenuation amount vmuai 78 79 v in = 2vrms, f = 1khz, amp = 5.5db, bw = jis-a evr = mute/evr = 0db -106 -85 db residual noise voltage vnar 78 79 amp = 5.5db, evr = mute rg = 0 , bw = jis-a -106 -80 dbv external control part i 2 c-bus high level input voltage v ih 88 89 2.5 v cc v i 2 c-bus low level input voltage v il 88 89 gnd 0.8 v fss output h voltage vhfss 27 serial control select fss out h, load = 10k external output resistor 470 recommended 10.6 11.1 11.6 v fss output m voltage vmfss 27 serial control select fss out m, load = 10k external output resistor 470 recommended 5.5 6.3 7.0 v fss output l voltage vlfss 27 serial control select fss out, load = 10k 0.0 0.1 0.5 v fss risinge time tfsslh 27 1.0 ms fb output h voltage vhfb 34 serial control select fb out h. load = 150 3.0 4.0 5.0 v fb output l voltage vlfb 34 serial control select fb out l. load = 150 0.0 0.2 0.4 v fb external control l range vlfbin 32 pin 32 input voltage range at which the pin 34 output becomes l 0.0 0.5 v fb external control h range vhfbin 32 pin 32 input voltage range when the pin 34 output becomes h 1.0 3.0 v external control output h voltage v exth 10 36 38 2k load for data 1 4.0 4.5 5.0 v external control output l voltage v extl 10 36 38 2k load for data 0 0.0 0.3 1.0 v internal reference regulator reg2.5v vreg25 2 100 pins 2 and 100 voltage 2.3 2.5 2.7 v reg9.0v vreg90 57 65 pins 57 and 65 voltage 8.7 9.0 9.3 v vre4.5 vreg45 49 pin 49 voltage 4.3 4.5 4.7 v
LV71081E no.a1610-6/31 package dimensions unit : mm (typ) 3349 graphical view of au dio block power supply sanyo : qip100ek(14x20) 14.0 17.2 20.0 0.22 23.2 130 31 50 51 80 81 100 0.8 0.65 (0.58) 0.15 0.1 (2.7) 3.0max 100k sw adc amp mute canal output rch input bias r-ch power supply of each block r-ch l-ch buffer standard eva standard adc amp standard 12dbamp standard l-ch 12db amp standard r mute bias l mute bias l-ch power supply of each block input buffer buffer 100k 100k 100k 100k sw buffer buffer eva buffer buffer buffer evr output 12db amp 9vreg 4.5vref p.mute 9vreg 56 55 50 46 57 49 dac_r_in vcr_r_in av3_r_in all 5v v cc = 11.6v 42 65 66 reg_gnd
LV71081E no.a1610-7/31 graphical view of the video block power supply * the thick line indicates the circuit operative in the power save mode. in the power save mode, 5v is applied to pin 42 (v cc 5_all), pin 84 (v cc 5v_vsw), and pin 94 (v cc _logic) only. input v cc 5v_vd v cc 5v_rgb rgb system lpf sw 6 gnd_vd 4 gnd_rgb 18 v cc 5v_vl 25 21 v cc 5v_vc 40 8 amp dr input line-out system lpf sw amp dr gnd_vc 29 input canal av1/2 system lpf sw gnd_vl amp dr 84 42 gnd_vsw 98 gnd_logic 96 input sw v cc 5v_vsw v cc 5v_all 94 serial v cc _logic 46 v cc 11.6v amp synchronous detection synchronous detection fb circuit operative in the p.s mode control system control system output stage output stage fss recording system
LV71081E no.a1610-8/31 block diagram 75 75 22 f 75 75 tuner v_in a v4(rear)r_in tuner2 ar in gnd_al 22 f av3(front)r_in + 75 100 f + 1.0 f 1.0 f 1.0 f 1.0 f 1.0 f 1.0 f + 1k 10 f + 10 f + 10 f + 10 f 1k 1k 1k + 25 26 27 28 29 30 19 20 21 22 23 24 13 14 15 16 18 7 8 10 11 4 6 86 85 84 83 82 81 92 90 89 88 87 98 96 94 100 46 49 39 40 42 44 34 36 37 38 32 av3(front)c_in v cc 12v_a v cc all 5v vcr y_in vcr c_in ref 4.5v av4(rear)y_in tuner2 v in v cc 5v_vc gnd_ref av1(16pin)fb_out ext_ctl3 ext_ctl4 c_sync_out slicer v cc 5v_vsw y/v_adc v_sync_out enc. c_in v_det_out sda_in scl_in v_det_in gnd_vsw enc. g/y_in gnd_logic enc. r/r-y_in v cc _logic enc. y_in reg 2.5 enc. b/b-y_in 56 55 54 53 52 62 61 60 59 58 57 68 67 66 65 64 63 74 73 72 71 70 69 80 79 78 77 76 75 a_dac_r_in vcr_r_in tuner1 ar_in av2(2pin) r_in av1(2pin) r_in tuner_al_in av2(6pin) l_in av1(6pin) l_in av4(rear)l_in tuner2 al rv3(front) l_in reg 9v ar n.c. n.c. gnd_reg reg 9v al a_dac_l_in vcr_l_in av2(1pin) r_out av2(3pin) l_out av1(1pin) r_out av1(3pin) l_out n.c. n.c. a_adc_r a_adc_l n.c. n.c. gnd_ar v cc 5v_vl n.c. n.c. n.c. n.c. n.c. n.c. n.c. gnd_vl av1(19pin) v_out av1(8pin) fss_out av2(19pin) v_out gnd_vc v_out (line_out) ext_ctl1 audio_mute_filter av1(11pin) g_out gnd-rgb v cc 5v_rgb av1(15pin) r/c_out sync_sep_lpf av1(7pin) b_out reg 2.5 gnd_vd av2(7pin) b_in v cc 5v_vd 0.1 f c_adc 75 75 75 75 75 1.0 f 1.0 f 1.0 f 1.0 f 1.0 f 1.0 f 1.0 f av3(front)y_in av3(front)v_in av2(20pin) v/y_in 0.1 f 0.1 f 0.1 f av2(15pin) r/c_in 0.1 f 0.01 f av2(11pin) g_in 0.1 f av2(16pin)fb_in av1(20pin)v_in 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 100k sa2r sa18r mute e d c b a 100k 100k 100k 100k 100k 100k 0.1 f 0.1 f 0.1 f 1.0 f av4(rear)v_in av4(rear)c_in 9 12 1 2 17 0.1 f 0.1 f 0.1 f 0.1 f 1 f 0.01 f ref reg bias bias clamp clamp clamp clamp clamp clamp clamp fss out serial ext ctl4 adc amp v-sync sep sync sep ext ctl3 45 47 43 sa3r e d c b a sa1r mute e d c b a sv2 sv17v sv14 sv12b sv1 mute mute e d c b a ba sv1 mute e d f c b a sa4r mute d c b a 12db sa2l sa18l mute e d c b a 100k 100k 100k 100k 100k 100k 100k reg sa3l e d c b a sa1l mute e d c b a mute a b c b f sa4l mute d c b a mute a bd f ce sv6 mute mute e d c b a sv6 sv5 e d c b a sv3 d c b a sv4 sv7 mute d c b a d c b a c b a 0v 5v 12db sv16 b a ab buf 51 mute lpf buf mute lpf buf mute lpf buf adc amp mute lpf lpf bias reg1 reg ext ctl1 6mhz 0db 0db 6db /0db 0db/ -12db 0db/ -12db bias 6db 6db 6db 6db sv13b mute a bd f ce e 6db sv11b 6db 93 clamp clamp clamp clamp clamp 6mhz clamp /bias 6mhz clamp /bias 6mhz clamp /bias 6mhz 95 97 bias 5 3 91 99 48 50 41 33 31 35 dr video signal detection
LV71081E no.a1610-9/31 test circuit + + + + 5v t26 t27 t26a + 100 h + 100 h open + 5v 100 h 47 f + 100 h 47 f + 11.6v + 100 h 47 f 75 75 10k 470 t30 t29 t17 t13 t17a open 75 75 t14 t14a t51 t24 t22a open 75 75 22 f t24a t20a t28 t28a open 75 75 t30a 0.1 f 75 ttuner1 v_in av2(15pin) r/c_in av4(rear)r_in tuner2 l in gnd_al t31 t31a 0.1 f 75 t32 75 t36 2k t38 2k t33 t33a 0.1 f 75 t35 t35a 0.1 f 75 t37 t35a 0.1 f 75 t39 t40 t41 t39a 0.1 f 75 t41a 0.1 f 75 t47 t49 t47a 0.1 f 75 1k t43a 0.1 f 22 f 75 t45a 0.1 f 75 t48a 0.1 f 75 t50 av3(front)r_in 1k t34 75 75 + t23 open 75 75 75 75 100 f open + t20 open 75 75 22 f + t19 open 75 75 100 f 1 f + open 75 2k 75 100 f 1 f + t52 1k 1 f + t53 1k 1 f + t54 1k 1 f + t55 1k 1 f + t56 1k 1 f + t57 10 f + t58 1k 1 f + t59 1k 1 f + t60 1k 1 f + t61 1k 1 f + t62 1k 1 f + t63 1k 1 f + t64 1k 1 f + t65 10 f + t71a t71 10k 10 f + t78a t78 10k 10 f + t79a t79 10k 10 f + t76a 10k 1.5meg 4.7 f + t72a t72 10k 10 f + t73a t73 10k 10 f + t74a t74 10k 10 f + t77 t76 22 f + t12 t12a open 75 75 t9 t9a open 75 75 75 + 100 h t7 t7a t5 t4 t5a open 75 75 t11 t11a open 75 75 330 f + t22 75 75 open 0.01 f 0.1 f 75 t3 t2 t3a 0.1 f 75 t1 t1a 0.1 f 330 f + + 1 f + 25 26 27 28 29 30 19 20 21 22 23 24 13 14 15 16 17 18 7 8 9 10 11 12 1 2 3 4 5 6 86 85 84 83 82 81 92 91 90 89 88 87 98 97 96 95 94 93 100 99 45 46 47 48 49 50 39 40 41 42 43 44 33 34 35 36 37 38 31 32 av3(front)c_in v cc 11.6v_a v cc 5v_all vcr y_in vcr c_in ref 4.5v av4(rear)y_in tuner2 v in v cc 5v_vc av3(front)y_in av(rear)c_in gnd_ref av1(20pin)v_in av1(16pin)fb_out av4(rear)v_in ext_ctl3 av3(front)v_in ext_ctl4 av1(20pin) v/y_in av2(16pin)fb_in c_sync_out slicer_out v cc 5v_vsw dac v/y_out v_sync_out v_det_fil enc. c_in v_det_out sda_in scl_in v_det_in gnd_vsw enc. g/y_in gnd_logic enc. r/r-y_in v cc _logic enc. y_in reg 2.5v enc. b/b-y_in 56 55 54 53 52 51 62 61 60 59 58 57 68 67 66 65 64 63 74 73 72 71 70 69 80 79 78 77 76 75 a_dac r_in vcr r_in tuner1 r_in av2(2pin) r_in av1(2pin) r_in tuner_al_in av2(6pin) l_in av1(6pin) l_in rv4(rear)l_in tuner2 l in rv3(front) l_in reg 9v ar nc nc gnd_reg reg 9v al a_dag l_in vcr l_in av2(3pin) r_out av2(1pin) l_out av1(3pin) r_out av1(1pin) l_out nc nc a_adc r_out a_adc l_out rf_out gnd_ar v cc 5v_vl av1(19pin) v_out av1(8pin) fss_out av2(19pin) v_out gnd_vc y_out (line_out) gnd_yl c_out (line_out) v_out (line_out) ext_ctl1 y_out (component) nc audio_mute_filter av1(11pin) g_out gnd-rgb r-y_out v cc 5v_rgb av1(15pin) r/c_out sync_sep_lpf b-y_out av1(7pin) b_out reg 2.5va av2(11pin) g_in gnd_vd av2(7pin) b_out v cc 5v_vd + 100 h + 100 h t100 t98 0.01 f t99 t99a 0.1 f 75 t97 t97a 0.1 f 75 t96 t95 t95a 0.1 f 75 t93 t93a t92 t90 t89 t88 0.1 f 1 f 75 t91a 0.1 f 75 10k t86 10k t85 10k t83 10k t82 10k t81 dac c_out 10k
LV71081E no.a1610-10/31 cautions for use 1. drive capacity of video driver line and component outputs can drive tw o system through capacitive coupling. scart output can drive one system only through dc coupling. 2. application not using the sag correction function in the video driver with sag correction when the sag correction function is not to be used in the video driver with sag correction, short-circuit output and correction pins for output through capacitive coupling. application using sag correction function application without using sag correction function 3. treatment of the pin when audio rf_mod output is not used when rf mod out (pin76) is not used, it is recommended to pull up the alc filter pin (pin77) to v cc (11.6v). 4. audio mute this ic incorporates a mute transistor to reduce the pop noise of audio output when power is turned on/off. mute control can be made by serial control. 5. resistor to limit the audio input when the large signal is input in the input pin with power off, cross-talk between input and output occurs through the protective diode and parasitic elements. b ecause of the structure of lsi, such cr oss-talk is difficult to avoid. if cross-talk at a time of power off pres ents a problem, the cross-talk amount can be reduced by inserting the limiting resistor in the input. in this case, the input signal leve l changes depending on the resistance value. determine the constant while taking both the cross-ta lk amount and input level into account. 6. pin treatment when external control is not to be used when external control pins (pins 13, 36, and 38) are not used, pull-down to gnd is recommended. 7. pin treatment of n.c pin it is recommended to connect n.c. pins (pins 67, 68, 69, and 70) directly to the gnd. 8. audio 9v_reg pin external capacitance use the audio 9v_reg pins (pins 57 and 66) external capacitance of 10 f or more and with the equivalent series resistance component of 7 or less. 9. power application and disconnection sequences the recommended power application sequence to this ic is v cc _all5v (pin42) v cc 5v (pins 6, 8, 25, 40, 84 and 94), v cc 11.6v (pin46). (no particular order is established between v cc 5v and v cc 11.6v.) it is recommended to reverse the above sequence when power supply is turned off. + 75 100 f video output pin sag correction pin + 75 22 f + 75 1000 f video output pin sag correction pin 75
LV71081E no.a1610-11/31 serial control table * indicates initial. address 8 7 6 5 4 3 2 1 remarks sv1 0 0 0 v (av2) * 0 0 1 y+c mix (enc) pb 0 1 0 y (enc) pb (scart y/c) 0 1 1 y (vcr) pb (vcr scart y/c) 1 0 0 cv (vcr) pb (vcr) 1 0 1 mute sv1 1 1 * prohibit sv2 0 0 0 v (av1) * 0 0 1 v (tu) 0 1 0 y+c mix (enc) pb 0 1 1 cv (vcr) pb (vcr) 1 0 0 mute sv2 1 0 1 and after prohibit sv3 0 0 v (av1) 0 1 v (av2) * 1 0 v (tu) group 1 00000001 video canal-sw video sv3 1 1 y (vcr) pb address 8 7 6 5 4 3 2 1 remarks sv4 0 0 v (av3) 0 1 v (av4) 1 0 sv3-out * sv4 1 1 sv5/6 mix sv5 sv6 0 0 0 y (av3) c (av3) front 0 0 1 y (av4) c (av4) rear 0 1 0 y (av2) c (av2) scart-yc 0 1 1 y (vcr) c (vcr) 1 0 0 mute mute * sv5/6 1 0 1 and after prohibit prohibit sv7 00 y 01 cv 10 mute * sv7 11 mute sv16 0 through * group 2 00000010 video input-sw sv16 note 1) 1 clamp input fixed note 1) g2d8/g3d8 = ? 11 ? is prohibited. follow the av2 (16) fb_in (pin32) control in case of through. av2_16pin sv16 h a : clamp input (rgb) l b : bias input (component)
LV71081E no.a1610-12/31 address 8 7 6 5 4 3 2 1 remarks 0 x = 12mhz * 12/27mhz lpf sw 1 x = 27mhz sv11b sv12b sv13b 0 according to g3d3/d4/d5 control rgb output 1 av2_r av2_g av2_b f : av2_rgb (external) * 0 0 0 n/a n/a n/a * 0 0 1 n/a n/a n/a 0 1 0 n/a n/a n/a 0 1 1 n/a n/a n/a 1 0 0 n/a n/a n/a 1 0 1 n/a n/a n/a n/a 1 1 0 and after prohibit prohibit prohibit sv11b sv12b sv13b 0 0 0 enc_r enc_g enc_b a : enc_rgb (6mlpf) * 0 0 1 mute mute mute b : mute 0 1 0 enc_c mute mute c : enc_c 0 1 1 vcr_c mute mute d : vcr_c 1 0 0 mute mute mute e : mute 1 0 1 av2_r av2_g av2_b f : av2_rgb (external) sv11b sv12b sv13b * effective at g3d2 = ? 0 ? 1 1 0 and after prohibit prohibit prohibit sv14 0 cv (pb) pb sv14 1 mute * 0 n/a n/a n/a 1 mute mute * sv16 0 through group 3 00000011 video other-1 sv16 note 1) 1 bias input fixed * note 1) g2d8/g3d8 = ? 11 ? is prohibited. follow the av2 (16) fb_in (pin32) control in case of through. av2_16pin sv16 h a : clamp input (rgb) l b : bias input (component)
LV71081E no.a1610-13/31 address 8 7 6 5 4 3 2 1 remarks sv17 (v/c/y) sa17 (l/r) 0 y+c mix (enc) audio (dac) pb (dvd) * sv17 dvd/vcr note 2) 1 y+c mix (vcr) audio (vcr) pb (vcr) sv18 sa18 (l/r) 0 tuner1 tuner1 * sv18 tuner1/2 note 2) 1 tuner2 tuner2 swf 0 0 0 0 1 5v 1 0 through * fb av1 (16) 1 1 through fss-out 0 0 low (0.5v) * 0 1 mid (6.0v) 1 0 high (11.0v) fss av1 (8) note 3) 1 1 high (11.0v) slice amp gain 0 0db * slice amp 1 6db all mute (audio) 0 through group 4 00000100 video & audio other-1 a-mute note 4) 1 mute pins 71 to 74 output mute * note 2) operates in video/audio interlock. note 3) same polarity as the av2 (16) fb_in (pin32) control in case of through. note 4) audio mute control rf_mod output : serial co ntrol mute, power-on_mute canal output : serial control mute, power-on_mute address 8 7 6 5 4 3 2 1 remarks sa1l sa1r 0 0 0 l (av2) r (av2) * 0 0 1 l (dac) r (dac) pb (dac) 0 1 0 l (dac) r (dac) pb (dac) 0 1 1 l (vcr) r (vcr) pb (vcr) 1 0 0 mute mute sa1l/r and after 1 0 1 prohib it prohibit sa2l sa2r 0 0 0 l (av1) r (av1) * 0 0 1 l (tu) r (tu) 0 1 0 l (dac) r (dac) pb 0 1 1 l (vcr) r (vcr) pb 1 0 0 mute mute sa2l/r 1 0 1 and after prohibit prohibit sa4l sa4r 0 0 l (av3) r (av3) 0 1 l (av4) r (av4) 1 0 sl3 out sr3 out * group 5 00000101 audio canal-sw sa4l/r 1 1 mute mute
LV71081E no.a1610-14/31 address 8 7 6 5 4 3 2 1 remarks sa3l sa3r 0 0 0 l (av1) r (av1) 0 0 1 l (av2) r (av2) * 0 1 0 l (tu) r (tu) 0 1 1 l (dac) r (dac) pb 1 0 0 l (vcr) r (vcr) sa3l/r and after 1 0 1 prohib it prohibit 0 n/a n/a 1 n/a * 0 0 n/a 0 1 n/a * 1 0 n/a n/a 1 1 prohibit adc-amp-gain 0 0 6.0db 0 1 5.5db * 1 0 5.0db group 6 00000110 audio input-sw mute adc-amp 1 1 prohibit address 8 7 6 5 4 3 2 1 remarks audio evr (l) 0 0 0 0 0 0 0db 0 0 1 1 0 0 -12db 1 1 1 1 1 1 mute pin 78 output mute * audio evr-l other than above prohibit ext_ctl1 (pin13) 0 l general purpose out1 general purpose 1 1 h * r/r-y_in (pin95) g/y_in (pin97) b/b-y_in (pin99) input changeover 0 bias input clamp input bias input component group 7 00000111 changeover of video input bias/clamp 1 clamp input clamp input clamp input rgb * address 8 7 6 5 4 3 2 1 remarks audio evr (r) 0 0 0 0 0 0 0db 0 0 1 1 0 0 -12db 1 1 1 1 1 1 mute pin 79 output mute * audio evr-r other than above prohibit ext_ctl3 (pin36) 0 l general purpose out3 * general purpose 3 1 h ext_ctl4 (pin38) 0 l general purpose out4 * group 8 00001000 general purpose 4 1 h
LV71081E no.a1610-15/31 serial control specification 1. slave address 2. data transfer manual : [1] is high level. [0] is low level. i 2 c-bus control system is adopted in sw lsi. sw lsi is controlled by scl (serial cloc k) and sda (serial data) at first, please set up the start condition *1 by these two terminals (scl and sda). and next, please input the 8bits data, which should be synchronized with scl in to sda terminal. still more, please give priority to high rank bit at data transfer order (msb lsb). the 9th bit is called as ack (acknowle dge), sw lsi sends [0] to the sda terminal during scl [1] period. so, please open the port of microprocessor during this period. LV71081E adopt auto-increment, so you input only first group-address an d you can transfer data in order. as thus the data transfer stop condition *2 is finished. *1 sda rise up during sci is [1] *2 sda fall down during scl is [1] 3. transfer data format the transfer data is composed by star t condition, slave address, group address *1 , data, and stop condition. after setting up the start condition, please transfer the sl ave address (regulated as ?1001000? in sw lsi). group and next control data *2 (please see the fig.1) slave address is composed by 7bits, and this bit 8th bit *3 should be set as [0]. the both of group address and control data are composed by 8bits, and the one control action is defined with combination of these two data. and if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. the data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. but LV71081E adopt auto-increment, for example you can stop to transfer stop co ndition after group 2 data. if you want to stop transfer action, pleas e transfer the stop condition without fail. *1/2 there are 8 control groups. *3 this 8th bit called as r/w bit, and this bit shows the data transmission di rection. [0] means send mode (accept mode with sw lsi) and [1] means accept mode (send m ode with sw lsi) fundamentally. but sw lsi is not equipped with such a data out function, please keep this bit as [0]. fig. 1 data structure 1 msb slave receiver one-way communication (this ic is dedicated to receive) lsb 0010100 r/w ack ack ack ..... stop condition start condition acknowledge start condition slave address group address control data stop condition
LV71081E no.a1610-16/31 4. initialize and others sw lsi is initialized as the following mode for ci rcuit protection. please see ?serial control table?. characteristics of the sda and scl 1/0 stages for sw lsi parameter symbol min max unit low level input voltage v il 0 0.8 v high level input voltage v ih 3.0 5.0 v low level output current i ol 3.0 ma scl clock frequency f scl 400 khz set-up time for a repeated start condition t su : sta 0.6 s hold time start condition. after this peri od, the first clock pulse is generated. t hd : sta 0.6 s low period of the scl clock t low 1.3 s rise time of both sda and sdl signals t r 0 0.3 s high period of the scl clock t high 0.6 s fall time of both sda and sdl signals t f 0 0.3 s data hold time: t hd : dat 0 0.9 s data set-up time t su : dat 100 ns set-up time for stop condition t su : sto 0.6 s bus fredd time between a stop and start condition t buf 1.3 s fig.2 definition of timing. t su :sto t su :dat t f t r t hd :dat t low t high t hd :sta t su :sta scl (86pin) sda (87pin) t buf
LV71081E no.a1610-17/31 pin function pin no. pin name dc voltage signal wave form in put/out put form 1.6v r 0.7vp-p 1.6v p1 av2r/c_in 2.1v chroma 0.7vp-p 2.1v 20k 1k 4k 4k 300 300 1 p2 reg 2.5va 2.5v dc 100 50 22.8k 23k 18.5k 18.5k 910 30k 13k 6.8k 10pf 1k 2 p3 av2 g_in 1.6v g 0.7vp-p 1.6v 1k 4k 4k 300 300 3 p4 gnd_vd p5 av2 b_in 1.6v b 0.7vp-p 1.6v 1k 4k 4k 300 300 5 p6 v cc 5v_vd p7 n.c. p8 v cc 5v_rgb continued on next page.
LV71081E no.a1610-18/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form 0.5v r 1.4vp-p 0.5v p9 av1 r/c_out 1.7v chroma 1.4vp-p 1.7v 200 100 2k 10.7k 10k 1.25pf 3.3pf 1.25pf 9 p10 sync_sep_lpf 1.0v y 1.0vp-p 2.2v 40k 500 500 8pf 10 p11 n.c. p12 av1 b_out 0.5v b 1.4vp-p 0.5v 200 100 2k 10.7k 10k 1.25pf 3.3pf 1.25pf 12 p13 ext_ctl1 0v 5v 13 p14 n.c. p15 n.c. p16 audio_mute_ filter 500 16 60k 140k continued on next page.
LV71081E no.a1610-19/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p17 av1 g_out 0.5v g 1.4vp-p 0.5v 200 100 2k 10.7k 10k 1.25pf 3.3pf 1.25pf 17 p18 gnd_rgb p19 n.c. p20 n.c. p21 gnd_vl p22 n.c. p23 v_out (line_out) 0.7v video 2.0vp-p 0.7v p24 v_sag_in (line_out) 0.7v video 2.0vp-p 0.7v 100 100 2k 10.4k 10k 1k 100k 3pf 3pf 3pf 23 24 p25 v cc 5v_vl 0.5v video 2.0vp-p 0.5v p26 av1 v_out 0.5v y 2.0vp-p 0.5v 200 100 2k 10.7k 10k 1.25pf 3.3pf 1.25pf 26 p27 av1 fss_out low : 0.5v midol : 6.0v high : 11.1v dc 100k 27 p28 av2 v_out 0.5v video 2.0vp-p 0.5v 200 100 2k 10.7k 10k 1.25pf 3.3pf 1.25pf 28 p29 gnd_vc continued on next page.
LV71081E no.a1610-20/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p30 tuner1 v_in 1.6v video 1.0vp-p 1.6v 1k 4k 4k 300 300 30 1.6v video 1.0vp-p 1.6v p31 av2 v/y_in 1.6v y 1.0vp-p 1.6v 1k 4k 4k 300 300 31 p32 av2 fb_in 0v 2v 1k 32 p33 av1 v_in 1.6v video 1.0vp-p 1.6v 1k 4k 4k 300 300 33 p34 av1 fb_out l : 0v h : 3.8v through :0/3.8v 0v 3.8v 100k 1k 1k 10 1k 1k 34 continued on next page.
LV71081E no.a1610-21/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p35 av4 v_in 1.6v video 1.0vp-p 1.6v 1k 4k 4k 300 300 35 p36 ext_ctl3 0v 5v 36 p37 av3 v_in 1.6v video 1.0vp-p 1.6v 1k 4k 4k 300 300 37 p38 ext_ctl4 0v 5v 38 1.6v y 1.0vp-p 1.6v p39 av4 y_in/ tuner2 v_in 1.6v video 1.0vp-p 1.6v 1k 4k 4k 300 300 39 p40 v cc 5v_vc continued on next page.
LV71081E no.a1610-22/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p41 av3 y_in 1.6v y 1.0vp-p 1.6v 1k 4k 4k 300 300 41 p42 v cc 5v_all 5v dc p43 av4 c_in 2.1v chroma 0.7vp-p 2.1v 1k 4k 20.3k 300 43 p44 gnd_ref 0v dc p45 av3 c_in 2.1v chroma 0.7vp-p 2.1v 1k 4k 20.3k 300 45 p46 v cc 11.6v_a 11.6v dc p47 vcr y_in 1.6 y 1.0vp-p 1.6v 1k 4k 4k 300 300 47 p48 vcr c_in 2.1v chroma 0.7vp-p 2.1v 1k 4k 20.3k 300 48 continued on next page.
LV71081E no.a1610-23/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p49 ref 4.5v 4.5v 1k 60k 60k 57 49 p50 av3 r_in 4.5v max 5.6vp-p 4.5v 50 500 100k 4.5v p51 av4 r_in/ tuner2 r_in 4.5v max 5.6vp-p 4.5v 51 500 100k 4.5v p52 av1 r_in 4.5v max 5.6vp-p 4.5v 52 500 100k 4.5v p53 av2 r_in 4.5v max 5.6vp-p 4.5v 53 500 100k 4.5v continued on next page.
LV71081E no.a1610-24/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p54 tuner1 r_in 4.5v max 5.6vp-p 4.5v 54 500 100k 4.5v p55 vcr r_in 4.5v max 5.6vp-p 4.5v 55 500 100k 4.5v p56 a_dac r_in 4.5v max 5.6vp-p 4.5v 56 500 100k 4.5v p57 reg 9v ar 9v dc 57 100 50 141k 23k p58 av3 l_in 4.5v max 5.6vp-p 4.5v 58 500 100k 4.5v continued on next page.
LV71081E no.a1610-25/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p59 av4 l_in/ tuner2 l_in 4.5v max 5.6vp-p 4.5v 59 500 100k 4.5v p60 av1 l_in 4.5v max 5.6vp-p 4.5v 60 500 100k 4.5v p61 av2 l_in 4.5v max 5.6vp-p 4.5v 61 500 100k 4.5v p62 tuner1 l_in 4.5v max 5.6vp-p 4.5v 62 500 100k 4.5v p63 vcr l_in 4.5v max 5.6vp-p 4.5v 63 500 100k 4.5v p64 a_dac l_in 4.5v max 5.6vp-p 4.5v 64 500 100k 4.5v continued on next page.
LV71081E no.a1610-26/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p65 reg 9v al 9v dc 65 100 50 141k 23k p66 gnd_reg 0v dc p67 n.c. p68 n.c. p69 n.c. p70 n.c. p71 av1 l_out 4.5v max 5.6vp-p 4.5v 20k 4.5v 100 700 71 p72 av1 r_out 4.5v max 5.6vp-p 4.5v 20k 4.5v 100 700 72 p73 av2 l_out 4.5v max 5.6vp-p 4.5v 20k 4.5v 100 700 73 continued on next page.
LV71081E no.a1610-27/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p74 av2 r_out 4.5v max 5.6vp-p 4.5v 20k 4.5v 100 700 74 p75 gnd_ar 0v dc p76 n.c. p77 n.c. p78 a_dac l_out 4.5v max 5.6vp-p 4.5v 78 100 p79 a_dac r_out 4.5v max 5.6vp-p 4.5v 79 100 p80 gnd_al p81 dac c_out 2.1v 0.7vp-p 2.1v 500 81 500 a p82 v_sync_out 0.3v 4.7v 82 300 300 continued on next page.
LV71081E no.a1610-28/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form 1.0v y 1.0vp-p 1.0v p83 dac v/y_out 1.0v video 1.0vp-p 1.0v 500 500 a 83 p84 v cc 5v_vsw 1.0v y max 2.0vp-p or 1.0vp-p 1.0v p85 slicer_out 1.0v video max 2.0vp-p or 1.0vp-p 1.0v 500 500 a 85 p86 c_cync_out 0.3v 4.7v 86 300 300 p87 v_det_in 0.3v 4.7v 50 a 87 10k 25k p88 scl_in 5v 1.0v 2.3v 50k 30k 88 continued on next page.
LV71081E no.a1610-29/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form p89 sdl_in 5v 1.0v 2.3v 50k 30k 89 p90 v_det_out 4.7v with signal 0v without signal dc 90 300 300 p91 enc. c_in 2.1v chroma 0.7vp-p 2.1v 1k 4k 20.3k 300 91 p92 v_det_fil dc 1k 1k 92 200 1k 60 a p93 enc. y_in 1.6v y 1.0vp-p 1.6v 4k 4k 300 300 93 1k p94 v cc _logic continued on next page.
LV71081E no.a1610-30/31 continued from preceding page. pin no. pin name dc voltage signal wave form in put/out put form 1.6v r 0.7vp-p 1.6v p95 enc. r/ r-y_in 2.1v r-y 0.7vp-p 2.1v 4k 4k 300 20k 300 95 60 a 1k p96 gnd_logic 1.6v g 0.7vp-p 1.6v p97 enc. g/y_in 1.6v y 1.0vp-p 1.6v 4k 4k 300 300 97 1k p98 gnd_vsw 1.6v b 0.7vp-p 1.6v p99 enc. b/ b-y_in 2.1v b-y 0.7vp-p 2.1v 4k 4k 300 20k 300 99 1k p100 reg 2.5v 2.5v dc 100 100 50 22.8k 23k 1k 6.8k 10pf 18.5k 18.5k 13k 30k 910
LV71081E ps no.a1610-31/31 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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